RISC-V RTL Lead: Microarchitecture & AI-Driven Design

Mirafra Technologies; California (MO); On-site; USD 120,000 - 170,000; Full time

Job summary

Mirafra Technologies is seeking a CPU design engineer to define and develop microarchitecture specifications for RISC-V cores, including branch predictor, rename, instruction scheduling, vector execution, and load/store units.

You will own RTL quality and verification strategy, apply RTL optimization to meet PPA goals, utilize AI tools to accelerate design, and mentor junior engineers.

Qualifications

• Degree in EE/CE/CS or related field required.
• Proven track record designing high‑performance CPU RTL for RISCV/Arm/x86/PWR/SPARC.
• Deep understanding of CPU microarchitecture and PPA trade-offs.
• Strong verification strategy across simulation and formal methods.

Responsibilities

• Define microarchitecture specifications for RISC-V CPU units (branch predictor, rename, instruction scheduling, vector execution, load/store).
• Develop RTL and supervise verification environment; apply RTL optimization to meet PPA targets.
• Mentor junior engineers and promote AI-assisted design practices.
• Analyze PPA to meet power, performance, and area targets.

Skills

Verilog

SystemVerilog

VHDL

CPU RTL design

RISC-V

Education

Bachelor's/Master's/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Mirafra Technologies is seeking a CPU design engineer to define and develop microarchitecture specifications for RISC-V cores, including branch predictor, rename, instruction scheduling, vector execution, and load/store units.

You will own RTL quality and verification strategy, apply RTL optimization to meet PPA goals, utilize AI tools to accelerate design, and mentor junior engineers.