RISC-V CPU Architect & RTL Lead - SoC Design

JDWK; Austin, Northern (TX, KY); Hybrid; USD 170,000 - 210,000; Full time

Benefits offered by this job

Flexible work arrangements

Competitive compensation

Job summary

JDWK Inc. invites a seasoned CPU RTL Lead to own the RISC-V core development from architecture to synthesizable RTL. You will evaluate open-source cores, define architectural tradeoffs, and implement new features within a startup environment.

You’ll oversee verification, synthesis, and performance analysis flows for the CPU subsystem. You’ll work hands-on with SystemVerilog, collaborate with SoC and firmware teams, mentor engineers, and help shape the silicon roadmap with a high-impact,

Qualifications

• 7+ years of RTL design experience with at least one CPU or DSP core from concept to silicon.
• Strong understanding of CPU microarchitecture including pipelines, branch prediction, hazards, caches, MMUs and power domains.
• Proficiency in SystemVerilog/Verilog RTL design, simulation, and synthesis.
• Experience with EDA tools (Synopsys, Cadence or open-source flows) for synthesis and linting.
• Solid verification methodologies (UVM, formal verification, or constrained-random testing).

Responsibilities

• Own the RISC-V CPU microarchitecture and RTL implementation, including pipeline and interfaces.
• Evaluate and compare open-source RISC-V cores for performance, scalability, and design quality.
• Architect enhancements or new cores tailored to application domains and system-level requirements.
• Develop and maintain synthesizable RTL in SystemVerilog/Verilog.
• Define verification strategy and collaborate on UVM, formal or FPGA-based validation of the core.
• Optimize for PPA targets through microarchitectural tuning and synthesis feedback.
• Collaborate with SoC, memory and firmware teams for seamless integration.
• Establish and maintain coding standards, linting and CI flows for RTL and verification.
• Mentor engineers and help build a small front-end design team.

Skills

RTL design

CPU microarchitecture

SystemVerilog

Verification

Cross-functional collaboration

Startup environment

Tools

Synopsys Cadence

Open-source flows

Job description

JDWK Inc. invites a seasoned CPU RTL Lead to own the RISC-V core development from architecture to synthesizable RTL. You will evaluate open-source cores, define architectural tradeoffs, and implement new features within a startup environment.

You’ll oversee verification, synthesis, and performance analysis flows for the CPU subsystem. You’ll work hands-on with SystemVerilog, collaborate with SoC and firmware teams, mentor engineers, and help shape the silicon roadmap with a high-impact,