Senior CPU RTL Architect & Microarchitecture Lead

SiFive; Santa Clara (CA); On-site; USD 206,000 - 251,000; Full time

Benefits offered by this job

Healthcare and retirement packages

Paid time off

Equity opportunities

Job summary

SiFive in Santa Clara, CA seeks an experienced CPU Microarchitecture/RTL design engineer to help craft industry-leading RISC-V cores. You will work on features, ISA extensions, and performance optimization within a Chisel/FIRRTL framework, collaborating with verification, physical design, and performance teams to deliver high-quality IP.

The role requires a BS/MS in CS/CE/EE, 7+ years of RTL design, Verilog/SystemVerilog/VHDL proficiency, and strong software engineering skills.

Qualifications

• BS/MS in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 7+ years of design experience.
• Academic or professional experience with CPU RTL design in instruction fetch, decode, branch prediction, caches, TLBs.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills including OO/FP, templated metaprogramming, compiler infrastructures, data modeling, and test-driven development.
• Attention to detail and teamwork.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute improvements for automatic configuration and documentation generation.
• Perform initial sandbox verification and collaborate with verification teams on test plans.
• Work with physical implementation to optimize for frequency, area, and power.
• Collaborate with performance modeling for exploration and optimization of performance goals.
• Share knowledge via documentation and participate in a culture of collaborative design.

Skills

RTL design

Verilog/SystemVerilog/VHDL

Software engineering

OOP/FP concepts

Team collaboration

Education

BS/MS in CS/CE/EE or related

Tools

Chisel/Scala

Bluespec

Git/Github/Jira/Confluence

Job description

SiFive in Santa Clara, CA seeks an experienced CPU Microarchitecture/RTL design engineer to help craft industry-leading RISC-V cores. You will work on features, ISA extensions, and performance optimization within a Chisel/FIRRTL framework, collaborating with verification, physical design, and performance teams to deliver high-quality IP.

The role requires a BS/MS in CS/CE/EE, 7+ years of RTL design, Verilog/SystemVerilog/VHDL proficiency, and strong software engineering skills.