RTL Lead role

Mirafra Technologies; California (MO); On-site; USD 120,000 - 170,000; Full time

Job summary

Mirafra Technologies is seeking a CPU design engineer to define and develop microarchitecture specifications for RISC-V cores, including branch predictor, rename, instruction scheduling, vector execution, and load/store units.

You will own RTL quality and verification strategy, apply RTL optimization to meet PPA goals, utilize AI tools to accelerate design, and mentor junior engineers.

Qualifications

• Degree in EE/CE/CS or related field required.
• Proven track record designing high‑performance CPU RTL for RISCV/Arm/x86/PWR/SPARC.
• Deep understanding of CPU microarchitecture and PPA trade-offs.
• Strong verification strategy across simulation and formal methods.

Responsibilities

• Define microarchitecture specifications for RISC-V CPU units (branch predictor, rename, instruction scheduling, vector execution, load/store).
• Develop RTL and supervise verification environment; apply RTL optimization to meet PPA targets.
• Mentor junior engineers and promote AI-assisted design practices.
• Analyze PPA to meet power, performance, and area targets.

Skills

Verilog

SystemVerilog

VHDL

CPU RTL design

RISC-V

Education

Bachelor's/Master's/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.

RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.

AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process.

Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team.

Qualifications:

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V.

Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…)

Deep understanding of CPU microarchitecture and PPA trade-off.

Basic understanding of RISC-V Architecture including V-extension is preferred.

Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.