RISC-V Debug, Trace & Profiling IP Architect

SiFive; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

SiFive is seeking a hardware design engineer in Austin, Texas, focused on developing leading debug, trace, and profiling IP for RISC-V architecture. The role involves collaborating with teams to enhance existing hardware and innovate new solutions.

The ideal candidate should possess 7+ years of experience in hardware design, specifically in debug and profiling architecture, with a strong commitment to quality and teamwork. SiFive promotes diversity and inclusion within its work environment.

Qualifications

• 7+ years of industry experience in hardware design for debug/trace/profiling.
• Knowledge in debug interfaces and specialist programming languages.
• Strong focus on high-quality design and collaboration skills.

Responsibilities

• Architect, design and implement debug and profiling hardware.
• Collaborate with various teams on architecture and specification.
• Ensure thorough documentation and knowledge sharing.

Skills

Debug, trace, and profiling architecture

Verilog/System Verilog/VHDL

Collaboration and teamwork

Attention to detail

CPU architectures

Software programming languages

Education

MS or PhD in EE, CE, CS or related field

Tools

Chisel/Scala

Git/Jira/Confluence

Job description

SiFive is seeking a hardware design engineer in Austin, Texas, focused on developing leading debug, trace, and profiling IP for RISC-V architecture. The role involves collaborating with teams to enhance existing hardware and innovate new solutions.

The ideal candidate should possess 7+ years of experience in hardware design, specifically in debug and profiling architecture, with a strong commitment to quality and teamwork. SiFive promotes diversity and inclusion within its work environment.