Lead Debug/Trace/Profiling Design Engineer

SiFive; Austin (TX); On-site; USD 170,000 - 225,000; Full time

Job summary

SiFive is seeking a hardware design technical lead to drive the development of industry‑leading debug, trace, and profiling IP for RISC‑V SoC designs.

The role covers architecture exploration, RTL generation, and open‑source framework integration, requiring strong collaboration across architecture, software and hardware teams.

Qualifications

• 7+ years leading architecture, microarchitecture and RTL design for debug/trace/profiling hardware.
• Experience with open RISC‑V and TileLink architectures is a plus.
• Proven ability to work across architecture, software and hardware teams.

Responsibilities

• Architect, design and implement debug, trace and profiling hardware.
• Collaborate with architecture, performance, software and hardware teams on exploration and specification.
• Create self-configuring RTL generators for extensive configurability.
• Integrate content into SiFive’s Chisel/FIRRTL framework for automated doc/testbench generation.
• Lead sandbox verification with the design verification team and develop test plans.
• Document knowledge and foster a culture of collaborative design.

Skills

Debug architecture

RTL design

Chisel/Scala

RISC‑V

JTAG

Git/Jira/Confluence

Team collaboration

Documentation

Programming languages (OO/functional)

Education

MS/PhD in EE/CE/CS

Tools

Chisel/FIRRTL

Job description

SiFive is seeking a hardware design technical lead to drive the development of industry-leading debug, trace, and profiling IP for RISC‑V SOC designs.

Key Challenges

• Designing the best debug, trace and profiling hardware in the world, based on the revolutionary open RISC-V and TileLink architectures.
• Mastering the art of designing hardware as configurable generators in a domain‑specific software language for elaborating digital logic.
• Working in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Job Responsibilities

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators such that elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.

Position Requirements

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience in debugging tools, profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of one or more of: Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
• MS/PhD in EE, CE, CS or a related technical discipline.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in France. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.