RISC-V Debug, Trace & Profiling IP Architect

SiFive; Boston (MA); On-site; USD 120,000 - 160,000; Full time

Job summary

SiFive is seeking a hardware design engineer in Boston, Massachusetts to lead enhancements in debug, trace and profiling hardware. This role focuses on developing innovative capabilities to support RISC-V architecture.

The ideal candidate will have over 7 years of experience in architecture and RTL design, proficiency in Verilog or VHDL, and strong collaborative skills. SiFive is an equal opportunity employer committed to diversity and inclusion.

Qualifications

• 7+ years of industry experience in RTL design for high-performance processors.
• Experience with hardware design tools and methodologies.
• Strong communication skills and a collaborative mindset.

Responsibilities

• Architect, design and implement debug, trace and profiling hardware.
• Collaborate with teams for architecture and microarchitecture exploration.
• Implement RTL generators for extensive configurability.
• Integrate designs into SiFive’s frameworks for improved configuration.
• Perform verification and maintain detailed documentation.

Skills

Debug, trace and profiling architecture

JTAG and cJTAG interfaces

CPU architectures

Debugging tools and profiling methods

Verilog/System Verilog/VHDL

Attention to detail

Team collaboration

Object-oriented programming

Chisel/Scala and Git

Education

MS or PhD in EE, CE, CS or a related technical discipline

Job description

SiFive is seeking a hardware design engineer in Boston, Massachusetts to lead enhancements in debug, trace and profiling hardware. This role focuses on developing innovative capabilities to support RISC-V architecture.

The ideal candidate will have over 7 years of experience in architecture and RTL design, proficiency in Verilog or VHDL, and strong collaborative skills. SiFive is an equal opportunity employer committed to diversity and inclusion.