Senior RTL Design Engineer - RISC-V CPU Microarchitecture

SiFive, Inc.; Santa Clara (CA); On-site; USD 206,000 - 251,000; Full time

Benefits offered by this job

Equity

Healthcare

Retirement plans

Paid time off

Job summary

SiFive, Inc. is seeking a CPU Microarchitecture/RTL design engineer to join a team creating industry-leading CPU cores based on RISC-V. You will design features, ISA extensions, and optimize performance within the Chisel/FIRRTL workflow.

The role requires 7+ years in CPU RTL design, proficiency in Verilog/SystemVerilog/VHDL, and strong software engineering skills. Collaboration across teams and a commitment to high-quality hardware are essential.

Qualifications

• BS/MS in computer science, computer engineering, electrical engineering or related field.
• 7+ years of design experience.
• CPU RTL design experience: fetch, decode, branch prediction, caches, TLBs.
• RTL design in Verilog, SystemVerilog or VHDL.
• Strong software engineering skills and teamwork.

Responsibilities

• Architect, design and implement features, improvements, and ISA extensions in RISC-V CPU cores using Chisel.
• Integrate content into Chisel/FIRRTL framework, enabling config/generation of tests and docs.
• Perform sandbox verification with the verification team and develop test plans.
• Collaborate with physical implementation to meet frequency, area and power goals.
• Work with performance modeling for exploration and optimization.
• Document knowledge and participate in collaborative design culture.

Skills

Chisel

RISC-V

Verilog

SystemVerilog

VHDL

C++

RTL design

Chisel/FIRRTL

Education

BS/MS degree in computer science, computer engineering, electrical engineering or related field

Tools

Git/Github

Jira

Confluence

Job description

SiFive, Inc. is seeking a CPU Microarchitecture/RTL design engineer to join a team creating industry-leading CPU cores based on RISC-V. You will design features, ISA extensions, and optimize performance within the Chisel/FIRRTL workflow.

The role requires 7+ years in CPU RTL design, proficiency in Verilog/SystemVerilog/VHDL, and strong software engineering skills. Collaboration across teams and a commitment to high-quality hardware are essential.