Senior RTL Design Engineer - RISC-V CPU Frontend

SiFive, Inc.; Santa Clara (CA); On-site; USD 158,760 - 194,040; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Equity compensation

Job summary

SiFive, Inc. in Santa Clara is seeking an experienced engineer to architect and implement features in RISC-V CPU core generators. This role demands proficiency in CPU RTL design and solid software engineering skills. A comprehensive benefits package is included, reflecting SiFive's commitment to employee well-being.

The ideal candidate will have a relevant degree and a collaborative mindset, contributing to a culture of high-quality design and teamwork.

Qualifications

• 3+ years of design experience related to CPU architecture.
• Experience with RISC-V or related architectures.
• Strong functional programming skills with experience in domain-specific languages.

Responsibilities

• Implement new features and performance improvements in RISC-V CPU core generators.
• Integrate design content into SiFive's Chisel/FIRRTL framework.
• Collaborate on verification test planning and documentation.

Skills

CPU RTL design expertise

Proficiency in Verilog/SystemVerilog/VHDL

Software engineering skills

Attention to detail

Teamwork skills

Education

BS/MS in computer science, engineering, or related

Tools

Git/GitHub

Jira

Confluence

Job description

SiFive, Inc. in Santa Clara is seeking an experienced engineer to architect and implement features in RISC-V CPU core generators. This role demands proficiency in CPU RTL design and solid software engineering skills. A comprehensive benefits package is included, reflecting SiFive's commitment to employee well-being.

The ideal candidate will have a relevant degree and a collaborative mindset, contributing to a culture of high-quality design and teamwork.