Lead Debug/Trace/Profiling Design Engineer

SiFive; Boston (MA); On-site; USD 120,000 - 150,000; Full time

Job summary

SiFive is looking for a hardware design technical lead based in Boston, Massachusetts. The ideal candidate will be responsible for designing industry-leading debug, trace, and profiling IP while enabling hardware design with agility. The successful applicant will collaborate with various teams and implement RTL generators that enhance configurability.

Candidates should have proven knowledge in CPU architectures and SoC design. This role is essential for driving RISC-V adoption across different applications.

Qualifications

• Extensive knowledge in designing debug, trace, and profiling hardware.
• Experience working with various performance and hardware teams.
• Capability in implementing RTL generators for hardware design.

Responsibilities

• Architect, design, and implement debug, trace, and profiling hardware.
• Collaborate with architecture and software teams for design specifications.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework.

Skills

Debug architecture knowledge

JTAG and cJTAG knowledge

CPU architectures and SoC design knowledge

Job description

SiFive is seeking a hardware design technical lead who is passionate about designing industry‑leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating a highly customizable line of processor cores with fast time‑to‑market by designing the hardware as highly configurable generators. Leveraging technology and ideas from the software industry, this role will enable hardware design with the speed and agility of software development, supporting our entire IP portfolio – Essential, Intelligence, Performance, and Automotive product lines.

Job Responsibilities

• Architect, design, and implement debug, trace, and profiling hardware.
• Work with architecture, performance, software, and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators so that elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to framework improvements to enable automatic configuration/generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge is shared via creation and maintenance of comprehensive documentation, fostering a culture of collaborative design.

Position Requirements

• Knowledgeable in debug, trace, and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, and cJTAG.
• Knowledgeable in CPU architectures, power management, and SoC design.