Debug/Trace/Profiling Design Engineer

SiFive; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

SiFive is seeking a hardware design engineer in Austin, Texas, focused on developing leading debug, trace, and profiling IP for RISC-V architecture. The role involves collaborating with teams to enhance existing hardware and innovate new solutions.

The ideal candidate should possess 7+ years of experience in hardware design, specifically in debug and profiling architecture, with a strong commitment to quality and teamwork. SiFive promotes diversity and inclusion within its work environment.

Qualifications

• 7+ years of industry experience in hardware design for debug/trace/profiling.
• Knowledge in debug interfaces and specialist programming languages.
• Strong focus on high-quality design and collaboration skills.

Responsibilities

• Architect, design and implement debug and profiling hardware.
• Collaborate with various teams on architecture and specification.
• Ensure thorough documentation and knowledge sharing.

Skills

Debug, trace, and profiling architecture

Verilog/System Verilog/VHDL

Collaboration and teamwork

Attention to detail

CPU architectures

Software programming languages

Education

MS or PhD in EE, CE, CS or related field

Tools

Chisel/Scala

Git/Jira/Confluence

Job description

Job Description

SiFive is seeking a hardware design engineer passionate about designing industry‑leading debug, trace and profiling IP to support the widespread adoption of RISC‑V as the architecture of choice for SOC designs. The engineer will lead enhancements of existing debug/trace/profiling hardware and develop new capabilities, collaborating with customers, partners, tools vendors and the RISC‑V International Association.

The Role

The focus of this position is on debug, trace, and profiling hardware. The successful applicant will address the following challenges:

• Design the best debug, trace and profiling hardware for open RISC‑V and TileLink architectures.
• Master designing hardware as configurable generators in a domain‑specific software language for elaborating digital logic.
• Work in a fast‑paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators so elements self‑configure to achieve extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Ensure knowledge is shared via creation and maintenance of great documentation and participation in a collaborative design culture.

Requirements

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG and cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
• MS or PhD in EE, CE, CS or a related technical discipline.

Additional Information

This position requires successful background and reference checks and satisfactory proof of your right to work in France. Employment is contingent upon verifying that employees are authorized for access to export‑controlled technology under applicable export control laws or that the company can obtain necessary export licenses or other approvals.

SiFive is an equal opportunity employer. SiFive celebrates diversity and is committed to creating an inclusive environment for all employees.