Research Engineer - System Technology & 3D/2.5D Packaging

Jobtailor; California (MO); On-site; USD 140,000 - 190,000; Full time

Job summary

Intel is seeking a Ph.D.-level candidate to develop and enhance System Technology Co-optimization (STCO) methodologies and perform system-level evaluations of advanced devices and integration schemes. You will evaluate 3D/2.5D packaging options and collaborate with diverse teams to push semiconductor innovation.

The role focuses on contributing to Intel's processing and packaging roadmap, with emphasis on IC design, layout, and multi-physics modelling using Python.

Qualifications

• Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design or similar.
• 1–2+ years of research in system architecture modelling, digital circuit analysis and design, or VLSI layout.
• Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsys Fusion Compiler.
• Preferred: System architecture design and modelling.
• Preferred: IC design, simulation, physical layout, and tape-out experience.
• Preferred: DRAM and SRAM circuit design and layout.
• Preferred: IC manufacturing flow and requirements.
• Preferred: 2.5D and 3D packaging technologies.
• Preferred: 3DIC design and simulation experience.
• Preferred: Python programming.

Responsibilities

• Develop and enhance System Technology Co-optimization (STCO) methodologies.
• Perform system-level evaluations of devices, interconnects, materials, and integration schemes.
• Evaluate 3D/2.5D dis-aggregation schemes for memory and logic stacking.
• Collaborate with diverse teams to drive semiconductor innovation.
• Contribute to Intel's semiconductor processing and packaging roadmap.

Skills

System Architecture Modeling

Digital Circuit Analysis

VLSI Physical Layout

Electronic Design Automation

3DIC Design And Simulation

Programming In Python

Multi-Physics Modeling

IC Design

Tape-Out Experience

3D/2.5D Packaging Technologies

Education

Active Ph.D. candidacy in Electrical Engineering / Electronics Engineering / Computer Architecture and Design

Tools

Cadence Virtuoso

Synopsys Fusion Compiler

Job description

Intel is seeking a Ph.D.-level candidate to develop and enhance System Technology Co-optimization (STCO) methodologies and perform system-level evaluations of advanced devices and integration schemes. You will evaluate 3D/2.5D packaging options and collaborate with diverse teams to push semiconductor innovation.

The role focuses on contributing to Intel's processing and packaging roadmap, with emphasis on IC design, layout, and multi-physics modelling using Python.