Research Engineer – System Technology, PhD Intern

Jobtailor; California (MO); On-site; USD 140,000 - 190,000; Full time

Job summary

Intel is seeking a Ph.D.-level candidate to develop and enhance System Technology Co-optimization (STCO) methodologies and perform system-level evaluations of advanced devices and integration schemes. You will evaluate 3D/2.5D packaging options and collaborate with diverse teams to push semiconductor innovation.

The role focuses on contributing to Intel's processing and packaging roadmap, with emphasis on IC design, layout, and multi-physics modelling using Python.

Qualifications

• Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design or similar.
• 1–2+ years of research in system architecture modelling, digital circuit analysis and design, or VLSI layout.
• Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsys Fusion Compiler.
• Preferred: System architecture design and modelling.
• Preferred: IC design, simulation, physical layout, and tape-out experience.
• Preferred: DRAM and SRAM circuit design and layout.
• Preferred: IC manufacturing flow and requirements.
• Preferred: 2.5D and 3D packaging technologies.
• Preferred: 3DIC design and simulation experience.
• Preferred: Python programming.

Responsibilities

• Develop and enhance System Technology Co-optimization (STCO) methodologies.
• Perform system-level evaluations of devices, interconnects, materials, and integration schemes.
• Evaluate 3D/2.5D dis-aggregation schemes for memory and logic stacking.
• Collaborate with diverse teams to drive semiconductor innovation.
• Contribute to Intel's semiconductor processing and packaging roadmap.

Skills

System Architecture Modeling

Digital Circuit Analysis

VLSI Physical Layout

Electronic Design Automation

3DIC Design And Simulation

Programming In Python

Multi-Physics Modeling

IC Design

Tape-Out Experience

3D/2.5D Packaging Technologies

Education

Active Ph.D. candidacy in Electrical Engineering / Electronics Engineering / Computer Architecture and Design

Tools

Cadence Virtuoso

Synopsys Fusion Compiler

Job description

• Develop and enhance System Technology Co-optimization (STCO) methodologies
• Perform system-level evaluations of novel devices, interconnects, patterning, materials, systems, and integration schemes
• Evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across product architectures
• Collaborate with diverse teams to drive innovation across various applications
• Contribute to Intel's semiconductor processing and packaging roadmap

Requirements

• Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design, or similar
• 1–2+ years of relevant research experience in system architecture modelling, digital circuit analysis and design, VLSI physical layout, electronic design automation, or multi-physics modeling of electronic materials or systems
• Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsys Fusion Compiler
• Preferred: System architecture design and modelling
• Preferred: IC design, simulation, physical layout, and tape-out experience
• Preferred: Familiarity with DRAM and SRAM circuit design and layout
• Preferred: Familiarity with integrated circuit manufacturing flow and requirements
• Preferred: Familiarity with 2.5D and 3D packaging technologies
• Preferred: 3DIC design and simulation experience
• Preferred: Good programming skills, preferably in Python

Core Competencies

Demonstrates expertise in System Technology Co-optimization methodologies and system architecture modeling, with a strong foundation in digital circuit analysis, VLSI physical layout, and electronic design automation. Proficient in IC design and familiar with advanced packaging technologies, contributing to innovative semiconductor solutions.

Highest-signal resume keywords

• Ph.D. Candidacy In Electrical Engineering
• System Architecture Modeling
• Digital Circuit Analysis And Design
• IC Design And Physical Layout
• Familiarity With Cadence Virtuoso

ATS Optimization Keywords

Hard Skills

• System Technology Co-optimization
• Digital Circuit Analysis
• VLSI Physical Layout
• Electronic Design Automation
• 3DIC Design And Simulation
• Programming In Python
• Multi-Physics Modeling
• IC Design
• Tape-Out Experience
• 3D/2.5D Packaging Technologies

Soft Skills

• Collaboration
• Innovation Drive

Industry Keywords

• Semiconductor Processing
• Integrated Circuit Manufacturing
• DRAM Circuit Design
• SRAM Circuit Design

Tools & Technologies

• Cadence Virtuoso
• Synopsys Fusion Compiler