Remote Senior DV Engineer - SystemVerilog/UVM & C++

Piepeople Consulting Inc.; San Francisco (CA); Remote; USD 140,000 - 180,000; Full time

Job summary

Piepeople Consulting Inc. is seeking an Experienced Design Verification Engineer to support functional and system-level verification of complex designs. The role requires strong DV background with C++ functional validation and SystemVerilog/UVM-based RTL verification.

The ideal candidate will debug across software and RTL, analyze coverage, and ensure complete verification as designs move through implementation levels. This position is remote within Pacific Time hours.

Qualifications

• DV experience with functional validation.
• Hands-on SystemVerilog and UVM experience.
• RTL verification, timing, and system-level interactions knowledge.
• Experience with C++ verification or functional models.
• Debugging across C++ and RTL domains.
• Coverage analysis and coverage closure experience.
• Able to work remotely during Pacific Time hours.

Responsibilities

• Perform functional validation and design verification across multiple system levels.
• Develop and execute verification using SystemVerilog and UVM for RTL functionality and system interactions.
• Test and validate design behavior using C++ and RTL-based verification environments.
• Debug complex issues across C++ models and RTL implementations.
• Perform coverage analysis and coverage closure to identify verification gaps.
• Investigate discrepancies between design levels and ensure consistent behavior through transformations.
• Collaborate with design and engineering teams to reproduce, isolate, and resolve defects.

Skills

Design Verification

SystemVerilog

UVM

RTL verification

C++ verification

Coverage analysis

Debugging across C++ & RTL

Tools

SystemVerilog

UVM

Job description

Piepeople Consulting Inc. is seeking an Experienced Design Verification Engineer to support functional and system-level verification of complex designs. The role requires strong DV background with C++ functional validation and SystemVerilog/UVM-based RTL verification.

The ideal candidate will debug across software and RTL, analyze coverage, and ensure complete verification as designs move through implementation levels. This position is remote within Pacific Time hours.