Senior Design Verification Engineer - SystemVerilog/UVM

eInfochips (An Arrow Company); San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

401k with matching

Disability insurance

HSA/HRA options

Paid time off

Tuition reimbursement

Job summary

eInfochips, an Arrow company, is seeking a senior verification engineer with 6+ years of SystemVerilog HVL and C/C++, and 6+ years in UVM. You will contribute to full verification cycles, including testplans, BFM/driver/monitor/scoreboard development, and debugging.

This role is fully on-site in San Jose, CA, with opportunities to work with leading semiconductor partners. Proficiency in scripting (Make/Perl/Python) and experience with various protocols are a plus, and you will report progress

Qualifications

• 6+ years in System Verilog HVL and C/C++.
• 6+ years in UVM.
• Test plan development, BFM/Driver/Monitor/Scoreboard integration and coverage.

Responsibilities

• Develop test plans and BFM/Driver/Monitor/Scoreboard components.
• Stress and corner testing, failure debugging and coverage closure.
• Coordinate verification closure with the team.

Skills

SystemVerilog HVL

C/C++

UVM

SVTB/UVM

Debugging/Assertions

Scripting (Make/Perl/Python)

Tools

Subversion

Bugzilla

Job description

eInfochips, an Arrow company, is seeking a senior verification engineer with 6+ years of SystemVerilog HVL and C/C++, and 6+ years in UVM. You will contribute to full verification cycles, including testplans, BFM/driver/monitor/scoreboard development, and debugging.

This role is fully on-site in San Jose, CA, with opportunities to work with leading semiconductor partners. Proficiency in scripting (Make/Perl/Python) and experience with various protocols are a plus, and you will report progress