Senior Design Verification Engineer

Piepeople Consulting Inc.; San Francisco (CA); Remote; USD 140,000 - 180,000; Full time

Job summary

Piepeople Consulting Inc. is seeking an Experienced Design Verification Engineer to support functional and system-level verification of complex designs. The role requires strong DV background with C++ functional validation and SystemVerilog/UVM-based RTL verification.

The ideal candidate will debug across software and RTL, analyze coverage, and ensure complete verification as designs move through implementation levels. This position is remote within Pacific Time hours.

Qualifications

• DV experience with functional validation.
• Hands-on SystemVerilog and UVM experience.
• RTL verification, timing, and system-level interactions knowledge.
• Experience with C++ verification or functional models.
• Debugging across C++ and RTL domains.
• Coverage analysis and coverage closure experience.
• Able to work remotely during Pacific Time hours.

Responsibilities

• Perform functional validation and design verification across multiple system levels.
• Develop and execute verification using SystemVerilog and UVM for RTL functionality and system interactions.
• Test and validate design behavior using C++ and RTL-based verification environments.
• Debug complex issues across C++ models and RTL implementations.
• Perform coverage analysis and coverage closure to identify verification gaps.
• Investigate discrepancies between design levels and ensure consistent behavior through transformations.
• Collaborate with design and engineering teams to reproduce, isolate, and resolve defects.

Skills

Design Verification

SystemVerilog

UVM

RTL verification

C++ verification

Coverage analysis

Debugging across C++ & RTL

Tools

SystemVerilog

UVM

Job description

Experienced Design Verification Engineer to support functional and system-level verification of complex designs. This role requires a strong multi-level design verification background, with experience spanning C++ functional validation and SystemVerilog/UVM-based RTL verification.

The ideal candidate will be comfortable debugging issues across both software and RTL environments, analyzing coverage, and ensuring complete verification as designs move through different levels of implementation.

Key Responsibilities

• Perform functional validation and design verification across multiple levels of the system.
• Develop and execute verification using SystemVerilog and UVM for RTL functionality, timing, and system interactions.
• Test and validate design behavior using C++ and RTL-based verification environments.
• Debug complex issues across C++ models and RTL implementations to identify functional and timing problems.
• Perform coverage analysis and coverage closure to identify verification gaps and improve test completeness.
• Investigate discrepancies between different levels of the design and help ensure consistent behavior throughout the design transformation process.
• Collaborate with design and engineering teams to reproduce, isolate, and resolve defects.

Qualifications

• Strong experience in Design Verification (DV) and functional validation.
• Hands-on experience with SystemVerilog and UVM.
• Strong understanding of RTL verification, timing, and system-level interactions.
• Experience working with C++ verification or functional models.
• Strong debugging and problem-solving skills across both C++ and RTL domains.
• Experience with functional and code coverage analysis and coverage closure.
• Ability to work effectively in a remote engineering environment during Pacific Time working hours.