Design Verification (DV) engineer Job ID: 419219

Mega Cloud Lab; United States; Remote; USD 110,000 - 170,000; Full time

Job summary

Mega Cloud Lab is seeking an experienced Design Verification (DV) engineer for a remote opportunity in the United States. You will develop verification plans and drive DV activities for hardware IPs.

Responsibilities include building UVM-based testbenches, constrained-random stimulus, assertion checkers, and applying AI-driven techniques to improve productivity. Collaboration with Digital Design and Concept teams is essential.

Qualifications

• Experience in design verification of hardware IPs.
• Proficiency with UVM-based testbenches and constrained-random stimulus.
• Familiarity with assertion-based checkers and coverage metrics.
• Exposure to AI-assisted verification methods is a plus.

Responsibilities

• Develop a comprehensive verification plan based on hardware requirements.
• Design, integrate, and maintain UVM-based testbench components.
• Develop constrained-random test cases, sequences, and assertion-based checkers.
• Apply AI-based verification methods and productivity tools where appropriate.
• Execute the verification plan and participate in reviews with Digital Design and Concept teams.
• Analysis of coverage closure and generation of formal verification reports and metrics.

Skills

DV engineering

UVM

Constrained-random testing

Assertion-based checkers

AI-based verification

Tools

UVM

Job description

Position6 : Design Verification (DV) engineer

Location : Remote

Only USC/GC- W2

Experienced Design Verification (DV) engineer for an upcoming IP verification project.

Scope of Work:

• Development of a comprehensive verification plan based on hardware requirements.
• Design, integration, and maintenance of UVM-based testbench components.
• Development of constrained-random test cases, sequences, and assertion-based checkers.
• Application of AI-based verification methods and productivity tools where appropriate.
• Execution of verification plan and implementation reviews with our Digital Design and Concept teams.
• Coverage closure and detailed metrics analysis.
• Generation of formal verification reports and regular attendance at project alignment meetings.
• Development of a comprehensive verification plan based on hardware requirements.
• Design, integration, and maintenance of UVM-based testbench components.
• Development of constrained-random test cases, sequences, and assertion-based checkers.
• Application of AI-based verification methods and productivity tools where appropriate.
• Execution of verification plan and implementation reviews with our Digital Design and Concept teams.
• Coverage closure and detailed metrics analysis.
• Generation of formal verification reports and regular attendance at project alignment meetings.