Remote DV Engineer — SystemVerilog/UVM for Tapeout Signoff

IC Resources; United States; Remote; USD 110,000 - 150,000; Full time

Job summary

IC Resources is seeking Design Verification Engineers for contract, W2 roles in the United States to support tapeout of high‑speed interconnect chips. You will build and extend UVM testbenches, write test plans and sequences, and drive regressions to closure before fab.

Ideal candidates have 5+ years of DV experience with SystemVerilog/UVM, ownership of a block or subsystem through tapeout, and strong debugging skills. Familiarity with PCIe, Ethernet or DDR is a plus.

Qualifications

• 5+ years of DV experience with SystemVerilog and UVM.
• At least one tapeout where you owned a block or subsystem through to closure.
• Strong debugging instincts and ability to work to a fixed date.

Responsibilities

• Build and extend UVM testbenches at block and subsystem level.
• Write test plans, sequences, checkers and functional coverage.
• Run regressions, debug failures and collaborate with designers to close bugs.
• Drive code and functional coverage to signoff targets.
• Support gate level sims and final checks ahead of tapeout.

Skills

DV with SystemVerilog/UVM

Tapeout ownership

Debugging under fixed dates

PCIe/Ethernet/DDR/AMBA/AXI familiarity

Python/TCL scripting

Job description

IC Resources is seeking Design Verification Engineers for contract, W2 roles in the United States to support tapeout of high‑speed interconnect chips. You will build and extend UVM testbenches, write test plans and sequences, and drive regressions to closure before fab.

Ideal candidates have 5+ years of DV experience with SystemVerilog/UVM, ownership of a block or subsystem through tapeout, and strong debugging skills. Familiarity with PCIe, Ethernet or DDR is a plus.