Remote Senior ASIC RTL Design Engineering Manager

Cornelis Networks; San Jose (CA); On-site; USD 210,000 - 320,000; Full time

Benefits offered by this job

Equity

Cash incentives

Health benefits

Retirement plan

Open time off

Job summary

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead an RTL design team responsible for SoC flow from microarchitecture to tape-out. You will build and mentor a global engineering organization, align schedules, and drive cross‑functional execution with Architecture, Verification, Emulation, and Physical Design.

The role emphasizes hands‑on leadership, headcount planning, and strategic hiring while ensuring high‑quality RTL, timing closure, and scalable design methods.

Qualifications

• 15+ years in semiconductor industry with leadership experience.
• BS/MS in Computer Engineering, Electrical Engineering, or related field.
• Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams.
• Proven ability to lead large engineering organizations through multiple ASIC launches in a remote environment.
• Strong expertise in microarchitecture, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Exposure to PCIe, Ethernet, UCIe, UALink.

Responsibilities

• Own ASIC RTL delivery schedules across major milestones.
• Use data-driven insights to predict schedule risks and reallocate resources.
• Align RTL delivery with DV and emulation enablement and manage dependencies.
• Facilitate physical design handoffs and ensure high-quality RTL and constraints.
• Lead long-term headcount planning and global talent acquisition strategies.

Skills

RTL coding (Verilog/SystemVerilog)

Synthesis

STA/Timing closure

Physical Design

Design Verification

Microarchitecture development

Team leadership

Remote collaboration

Education

B.S./M.S. in Computer or Electrical Engineering or related field

Job description

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead an RTL design team responsible for SoC flow from microarchitecture to tape-out. You will build and mentor a global engineering organization, align schedules, and drive cross‑functional execution with Architecture, Verification, Emulation, and Physical Design.

The role emphasizes hands‑on leadership, headcount planning, and strategic hiring while ensuring high‑quality RTL, timing closure, and scalable design methods.