Senior ASIC RTL Design Engineer – Remote (US)

Saransh Inc; United States; On-site; USD 140,000 - 230,000; Part time

Job summary

Saransh Inc. is seeking a Senior ASIC RTL Design Engineer to contribute across the full silicon development lifecycle—from analysis to RTL, verification, and implementation. You will engage with a customer-facing role to define requirements and support PoC and production phases.

You will design synthesizable SystemVerilog/Verilog for high-performance compute subsystems, drive timing closure, and collaborate with multiple teams across the project lifecycle.

Qualifications

• Must have BSc/MSc in Electronics, Radio Engineering, Computer Engineering, or related field.
• Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals.
• Experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC).

Responsibilities

• Design synthesizable SystemVerilog/Verilog for high-performance compute subsystems: systolic arrays, vector/datapaths, on-chip memory, DMA engines, and control logic.
• Translate architecture specifications into RTL; drive timing closure and handoffs to synthesis, PD, and verification.
• Investigate and implement architectural/power optimizations: clock gating, power islands, DVFS, and datapath activity reduction.
• Build RTL-level power models; collaborate on power budgeting and convergence to chip-wide goals.
• Define and integrate chip-wide power management strategies: DVFS, idle/wake states, and thermal coordination.
• Integrate blocks at SoC/top level clock/reset domains, bus fabrics (AXI/CHI/NOC), and low-power design methodology.
• Partner with architects, PD, verification, firmware, and compiler/runtime teams on HW/SW co-design and ML kernel mapping.
• Support FPGA/emulation bring-up and post-silicon debug; analyze waveforms and propose ECOs.
• Strong ownership, scripting proficiency (Python/Tcl), and fluency with EDA flows (DC/Genus, PrimeTime, VCS/Xcelium, SpyGlass, Verdi).

Skills

RTL Design

SystemVerilog/Verilog

Power optimization

Python/Tcl scripting

VLSI/SoC fundamentals

Education

BSc/MSc in Electronics/Radio/Computer Engineering

Tools

DC/Genus

PrimeTime

VCS/Xcelium

SpyGlass

Verdi

Job description

Saransh Inc. is seeking a Senior ASIC RTL Design Engineer to contribute across the full silicon development lifecycle—from analysis to RTL, verification, and implementation. You will engage with a customer-facing role to define requirements and support PoC and production phases.

You will design synthesizable SystemVerilog/Verilog for high-performance compute subsystems, drive timing closure, and collaborate with multiple teams across the project lifecycle.