ASIC/RTL Design Engineer

TPI Global Solutions; San Jose (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

TPI Global Solutions in San Jose, CA seeks a Senior/Staff ASIC/RTL Design Engineer with 10+ years of end-to-end SoC experience to lead complex digital designs.

You will own RTL coding, micro-architecture, design flow, verification, synthesis, timing closure, silicon bring-up, and collaborate with ARM core teams and interfaces like PCIe, DDR4/5, Ethernet, DMA, SATA.

Qualifications

• 10+ years in ASIC/RTL/SoC design with end-to-end ownership.
• Strong RTL coding, architecture, and design-flow expertise.
• Experience with ARM cores and high-speed interfaces.

Responsibilities

• Lead end-to-end SoC design projects and reviews.
• Drive verification, synthesis, and timing closure.
• Coordinate silicon bring-up with cross-functional teams.

Skills

RTL coding

Micro-architecture

ASIC design flow

Verification & debug

Synthesis

Timing closure

ARM cores

PCIe hardware

DDR4/DDR5

Ethernet

DMA

SATA

silicon bring-up

Tools

Emulation

Physical design coordination

Job description

This is a Senior/Staff-level ASIC/RTL Design Engineer role requiring 10+ years of industry experience in end-to-end SoC design. The strongest candidates should have hands-on expertise in RTL coding, micro-architecture, ASIC design flow, verification/debug, synthesis, timing closure, and silicon bring-up, with experience leading complex digital designs.

Core requirements:

• 10+ years of ASIC/RTL/SoC Design experience.
• SoC architecture and micro-architecture development.
• Experience with complete ASIC design flow.
• Synthesis and timing closure.
• Experience with ARM cores.
• Knowledge of high-speed interfaces such as: PCIe, DDR/DDR4/DDR5, Ethernet, DMA, SATA.
• Experience working with physical design, software, emulation, and silicon bring-up teams.