Senior ASIC Design Engineer – High‑Speed Networking

Cornelis Networks; Austin (TX); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Health benefits

401(k) with company match

Open Time Off

Job summary

Cornelis Networks is seeking a Senior ASIC Design Engineer to develop high-performance SoCs in a remote position. The ideal candidate will have 8+ years of experience in digital design with proficiency in Verilog/System Verilog. Key responsibilities include implementing RTL designs and collaborating with verification teams. The role offers competitive compensation, including equity, cash, benefits, and a flexible work environment.

Qualifications

• 8+ years of post-college experience in digital design.
• Experience in RTL design for high-speed data paths.
• Proven ability in system-level debug and root cause analysis.

Responsibilities

• Implement RTL designs for high-speed data paths.
• Collaborate with verification engineers to create test plans.
• Support post-silicon validation and debug ASIC issues.

Skills

Verilog/System Verilog

Digital design

System-level debug

Networking protocols

Scripting languages (TCL, Python, Perl)

Education

B.S. or M.S. degree in Computer Engineering or Electrical Engineering

Tools

Design Compiler

Spyglass

PrimeTime

Job description

Cornelis Networks is seeking a Senior ASIC Design Engineer to develop high-performance SoCs in a remote position. The ideal candidate will have 8+ years of experience in digital design with proficiency in Verilog/System Verilog. Key responsibilities include implementing RTL designs and collaborating with verification teams. The role offers competitive compensation, including equity, cash, benefits, and a flexible work environment.