Remote Senior ASIC RTL Design Engineering Manager

cornelisnetworks; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity

Annual bonus

Health benefits

401(k) with company match

Job summary

Cornelis Networks seeks a Senior ASIC Design Engineering Manager to lead RTL implementation across SoC subsystems and drive tape-out milestones. You will manage a remote team, align DV/Emulation, and own headcount and organizational strategy to scale a world-class design organization.

The role requires hands-on RTL expertise, strong program execution, and experience coordinating Architecture, Design Verification, Emulation, and Physical Design across multiple projects in a dynamic remote setting.

Qualifications

• 15+ years in the semiconductor industry, with at least 5 years in people management.
• Deep understanding of interaction between Design, Verification, Emulation, and Physical Design teams.
• Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment.
• Strong technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Exposure to PCIe, Ethernet, UCIe, UALink.

Responsibilities

• Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans.
• Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track.
• Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently.
• Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations. Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones.
• Lead long-term headcount planning and organizational design for the ASIC department. Identify skill gaps and execute global talent acquisition strategies that support the product roadmap.

Skills

RTL design

Verilog/SystemVerilog

Synthesis

STA/timing closure

Physical design

Design verification

Leadership

Education

B.S./M.S. in Computer/Electrical Engineering

Tools

Emulation

Job description

Cornelis Networks seeks a Senior ASIC Design Engineering Manager to lead RTL implementation across SoC subsystems and drive tape-out milestones. You will manage a remote team, align DV/Emulation, and own headcount and organizational strategy to scale a world-class design organization.

The role requires hands-on RTL expertise, strong program execution, and experience coordinating Architecture, Design Verification, Emulation, and Physical Design across multiple projects in a dynamic remote setting.