Remote Senior ASIC Design Engineering Manager

Cornelis Networks; United States; On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Equity

Health benefits

401(k) with match

Job summary

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead and grow the RTL design team. You will manage full-lifecycle development of high-performance networking ASICs, with cross-functional collaboration across Architecture, Design Verification, Emulation, and Physical Design.

The role requires 15+ years in semiconductors, strong RTL and microarchitecture expertise, and demonstrated leadership in remote environments.

Qualifications

• 15+ years in the semiconductor industry with senior leadership experience.
• BS or MS in Computer Engineering, Electrical Engineering, or related field, or equivalent experience.
• Deep understanding of interaction between Design, Verification, Emulation, and Physical Design teams.
• Led large engineering orgs through multiple ASIC product launches in a remote environment.
• Strong technical expertise in microarchitecture, RTL coding (Verilog/SystemVerilog), synthesis, STA, physical design, and verification.
• Exposure to PCIe, Ethernet, UCIe, UALink or similar stacks.

Responsibilities

• Own ASIC RTL delivery schedules across major milestones and track progress.
• Use data-driven insights to predict schedule risks and allocate resources.
• Align RTL delivery with DV and emulation enablement; manage feedback and dependencies.
• Facilitate physical design handoffs; ensure RTL constraints minimize timing-closure iterations.
• Lead headcount planning and global talent acquisition for the ASIC department.

Skills

RTL design

Verilog/SystemVerilog

Synthesis

STA/timing closure

Physical design

Verification methodologies

Microarchitecture development

Leadership and management

Cross-functional coordination

Education

BS in Computer/Electrical Engineering

MS in related field

Tools

Emulation

Scripting for automation

Job description

Cornelis Networks is seeking a Senior ASIC Design Engineering Manager to lead and grow the RTL design team. You will manage full-lifecycle development of high-performance networking ASICs, with cross-functional collaboration across Architecture, Design Verification, Emulation, and Physical Design.

The role requires 15+ years in semiconductors, strong RTL and microarchitecture expertise, and demonstrated leadership in remote environments.