Senior ASIC Verification Lead (Remote)

cornelisnetworks; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity compensation

Health benefits

401(k) with company match

Open Time Off

Job summary

Cornelis Networks is seeking a Principal ASIC Verification Engineer to lead verification for high-performance SoCs used in AI and HPC interconnects. You will define verification strategy, drive UVM testbench development, and ensure coverage closure across blocks and sub-systems.

As a member of the leadership team, you will mentor engineers, steer test planning, and collaborate with design, emulation, software, and validation teams to deliver first-pass silicon success.

Qualifications

• 15+ years of experience with networking hardware verification.
• Proficiency with UVM/SystemVerilog and RTL verification.
• Experience with multi-clock domain SoCs and debugging using Verdi or equivalent.
• Experience with testbench development and coverage driven verification.
• Experience with version control systems like Git or SVN.

Responsibilities

• Define overall SOC level verification strategy and plan.
• Enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels.
• Develop and execute functional tests according to verification plans.
• Instrument TB for functional and code coverage and drive to closure.
• Collaborate with design, software, emulation and validation teams.

Skills

UVM/SystemVerilog

SoC verification

Bug debugging (RTL)

Testbench development

Git / SVN

Team leadership

Education

B.S. in Computer Engineering / CS / Electrical Engineering

M.S. in Computer Engineering / Computer Science / Electrical Engineering

Tools

VCS

Verdi

Git

SVN

Job description

Cornelis Networks is seeking a Principal ASIC Verification Engineer to lead verification for high-performance SoCs used in AI and HPC interconnects. You will define verification strategy, drive UVM testbench development, and ensure coverage closure across blocks and sub-systems.

As a member of the leadership team, you will mentor engineers, steer test planning, and collaborate with design, emulation, software, and validation teams to deliver first-pass silicon success.