Senior ASIC Verification Engineer - Remote SoC/UVM

Cornelis Networks; San Jose, Northern (CA, KY); Hybrid; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity

Health benefits

401(k) match

Open Time Off

Job summary

Cornelis Networks is seeking a Senior ASIC Verification Engineer to drive verification closure for high-performance SoCs used in AI and HPC interconnects. The role requires hands-on UVM/SystemVerilog, RTL debugging, test-plan development, and leadership across design, emulation and software teams.

This remote US-based position includes equity, health and retirement benefits, and a competitive total rewards package.

Qualifications

• 8+ years of experience in networking hardware verification.
• Hands-on experience with UVM/SystemVerilog.
• Experience with RTL debugging and bug fixes.
• BS in Computer Engineering, Computer Science, or Electrical Engineering.

Responsibilities

• Define SOC verification strategy and test plans.
• Develop UVM environments for RTL verification at block, unit, and SoC levels.
• Drive coverage closure and functional/test execution.
• Collaborate with design, software, emulation and silicon validation teams.

Skills

UVM/SystemVerilog

SoC verification

Git/SVN

BS in CE/CS/EE

Education

B.S. in Computer Engineering, Computer Science, or Electrical Engineering

Tools

Verdi

VCS

Job description

Cornelis Networks is seeking a Senior ASIC Verification Engineer to drive verification closure for high-performance SoCs used in AI and HPC interconnects. The role requires hands-on UVM/SystemVerilog, RTL debugging, test-plan development, and leadership across design, emulation and software teams.

This remote US-based position includes equity, health and retirement benefits, and a competitive total rewards package.