Quantum IC Substrate Layout Engineer — 2.5D/3D Packaging

Intel Corporation; Hillsboro, Northern (OR, KY); Hybrid; USD 122,000 - 173,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Job summary

Intel Corporation in Oregon invites an experienced Quantum IC Substrate Package Layout Design Engineer to join our Quantum Computing Group. You will design large form factor substrates, collaborate with SI/PI/thermal teams, and drive tapeouts with suppliers, delivering robust, manufacturable packaging solutions.

You will contribute to next-generation silicon quantum dot technology and stay at the forefront of semiconductor packaging innovations in a fast-paced research environment.

Qualifications

• BS or MS in Electrical/Computer Engineering with 3+ years (MS) or 5+ years (BS) in IC substrate design for CPU/GPU/SoC/ASIC.
• Experience with Siemens Xpedition design environment and workflow is required.
• Experience with high-speed signal routing and large form factor IC substrates is required.

Responsibilities

• Design of large form factor IC substrates using Siemens Xpedition.
• Coordinate with silicon testchip, SI, PI, thermal and system integration engineers to meet design requirements.
• Deliver design milestones and conduct design validation (DRC/LVS).
• Integrate advanced packaging (2.5D/3D) with IC substrate and manage tapeouts with suppliers.
• Present designs to stakeholders and stay current with packaging tech developments.

Skills

High-speed routing

Analytical thinking

Communication

Collaboration

Education

B.S. in Electrical/Computer Engineering

M.S. in Electrical/Computer Engineering

Tools

Siemens Xpedition

IC substrate tooling

Job description

Intel Corporation in Oregon invites an experienced Quantum IC Substrate Package Layout Design Engineer to join our Quantum Computing Group. You will design large form factor substrates, collaborate with SI/PI/thermal teams, and drive tapeouts with suppliers, delivering robust, manufacturable packaging solutions.

You will contribute to next-generation silicon quantum dot technology and stay at the forefront of semiconductor packaging innovations in a fast-paced research environment.