Quantum Packaging SI/PI Engineer - Shape Quantum Hardware

Intel Corporation

Hillsboro (OR)

On-site

USD 142,000 - 200,000

Full time

14 days+
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Job summary

Intel Corporation in Oregon is seeking an experienced Quantum Packaging SI/PI Engineer to model and simulate packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team.

The role emphasizes SI/PI modeling, validation, and optimization using tools like SIwave, HFSS, and ADS. Collaboration with hardware teams and stakeholders is essential to meet ambitious quantum packaging goals in a fast-paced research environment.

Qualifications

  • M.S. degree in Electrical Engineering, Physics or related field AND 3+ years of experience in SI/PI for packaging, silicon testchip, or other related hardware. OR Ph.D. degree in Electrical Engineering, Physics or related field with academic or work experience in the related areas.
  • The experience must include: SI/PI modeling, simulation, and optimization with simulation software such as SIwave, HFSS, ADS, and related.
  • SI/PI/thermal impact on IC substrate design choices.
  • Design experience with large form factor IC substrates.

Responsibilities

  • Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing.
  • Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams.
  • In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware.
  • System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements.
  • Deliver and disseminate design milestones to stakeholders.
  • Communicate designs in presentations and relevant documentation.
  • Stay current with the latest developments in packaging technology and design techniques by attending conferences and reading papers.

Skills

SI/PI packaging experience
Modeling & simulation
Cross-functional collaboration

Education

M.S. in Electrical Engineering or Physics or related field
Ph.D. in Electrical Engineering or Physics or related field

Tools

SIwave
HFSS
ADS
RaptorH/X

Job description

Intel Corporation in Oregon is seeking an experienced Quantum Packaging SI/PI Engineer to model and simulate packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team.

The role emphasizes SI/PI modeling, validation, and optimization using tools like SIwave, HFSS, and ADS. Collaboration with hardware teams and stakeholders is essential to meet ambitious quantum packaging goals in a fast-paced research environment.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Quantum Packaging Signal/Power Integrity (SI/PI) Engineer
Quantum Packaging Signal/Power Integrity (SI/PI) Engineer

Intel Corporation • Hillsboro (OR)

On-site
USD 142,000 - 200,000
Quantum Interposer Design Engineer: Silicon Qubit Packaging
Quantum Interposer Design Engineer: Silicon Qubit Packaging

Intel • Hillsboro (OR)

On-site
USD 142,000 - 200,000
Health benefits
Stock bonuses
Retirement plan
+1
Quantum Packaging Thermal Architect: Heat for Quantum Dots
Quantum Packaging Thermal Architect: Heat for Quantum Dots

Intel Corporation • Hillsboro (OR)

On-site
USD 142,000 - 200,000
Competitive pay
Stock bonuses
Health benefits
+2
Quantum Packaging Thermal Architect: Heat Design for Qubits
Quantum Packaging Thermal Architect: Heat Design for Qubits

Intel • Hillsboro (OR)

On-site
USD 142,000 - 200,000
Stock bonuses
Health benefits
Vacation
Quantum Packaging Thermal Architect
Quantum Packaging Thermal Architect

Intel • Hillsboro (OR)

On-site
USD 142,000 - 200,000
Stock bonuses
Health benefits
Vacation
Quantum Interposer Design Engineer
Quantum Interposer Design Engineer

Intel • Hillsboro (OR)

On-site
USD 142,000 - 200,000
Health benefits
Stock bonuses
Retirement plan
+1
Quantum Packaging Engineer - Die & Bonding
Quantum Packaging Engineer - Die & Bonding

Amazon Inc. • Omaha (NE), Northern (KY)

Hybrid
USD 75,000 - 131,000
Health insurance
RSUs
Sign-on bonus
Quantum Qubit Design Architect
Quantum Qubit Design Architect

Intel • Austin (TX)

On-site
USD 142,000 - 269,000
Stock bonuses
Health benefits
Retirement plan
ASIC Packaging SI/PI Engineer - Hybrid (San Jose)
ASIC Packaging SI/PI Engineer - Hybrid (San Jose)

Cisco • San Jose (CA)

On-site
USD 150,000 - 230,000
Medical, dental and vision insurance
401(k) with Cisco matching
Paid parental leave
+1
Senior Packaging SIPI Engineer — High‑Speed SerDes & SI/PI
Senior Packaging SIPI Engineer — High‑Speed SerDes & SI/PI

Qualcomm • San Diego (CA)

On-site
USD 202,000 - 302,000