Quantum Interposer Packaging Design Engineer

Intel Corporation; Hillsboro (OR); On-site; USD 142,000 - 200,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plan

Paid vacation

Job summary

Intel Corporation in Oregon seeks a Quantum Interposer Design Engineer to advance physical design and integration of interposers for quantum computing, collaborating with SI/PI, thermal, and system teams. The role emphasizes reliable design, validation, and clear technical communication in a fast-paced research setting.

The position expects a strong background in MS/PhD-level electrical engineering, advanced packaging, and Cadence Virtuoso, with a focus on silicon testchips and interposers.

Qualifications

• MS degree in Electrical Engineering with 5+ years in physical design of silicon testchips/interposers or related hardware.
• OR PhD with relevant experience in physical design, SI/PI, and packaging technologies.
• Cadence Virtuoso experience required.
• Understanding of SI/PI impact on physical design.
• Understanding of advanced packaging technologies.

Responsibilities

• Physical design and integration of interposers used within advanced packaging for quantum computing
• Collaborate with silicon testchip, SI/PI, thermal, and system integration engineers to meet design requirements
• Design validation and verification including DRC/LVS
• Deliver milestones and document designs for stakeholders
• Present designs to stakeholders and prepare technical documentation
• Keep current with packaging tech through conferences and literature

Skills

Communication skills

Analytical thinking

Collaboration

Adaptability

Quantum tech passion

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Virtuoso

Synopsys

Ansys

Job description

Intel Corporation in Oregon seeks a Quantum Interposer Design Engineer to advance physical design and integration of interposers for quantum computing, collaborating with SI/PI, thermal, and system teams. The role emphasizes reliable design, validation, and clear technical communication in a fast-paced research setting.

The position expects a strong background in MS/PhD-level electrical engineering, advanced packaging, and Cadence Virtuoso, with a focus on silicon testchips and interposers.