Quantum IC Substrate Layout Engineer (2.5D/3D Packaging)

Intel

Hillsboro (OR)

On-site

USD 122,000 - 173,000

Full time

3 days ago

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Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in Oregon is seeking a Quantum IC Substrate Package Layout Design Engineer to design large form factor IC substrates and drive packaging innovation. You will collaborate with SI/PI/thermal/system engineers to meet design requirements and deliver milestones across the project lifecycle.

The role requires 5+ years of substrate design experience (or 3+ with MS) and hands-on Siemens Xpedition expertise, with opportunities to work on 2.5D/3D packaging and tapeouts in a cutting‑edge

Qualifications

Degree in EE/CE or related field with required years of experience.
Experience in IC substrate design for CPU/GPU/SoC/ASIC.
Proficiency with Siemens Xpedition environment and workflow.

Responsibilities

Design IC substrates for large form factor packages.
Collaborate with silicon test, SI, PI, thermal, and system engineers.
Deliver milestones and documentation to stakeholders.
Perform design validation including DRC and LVS.
Integrate advanced packaging (2.5D/3D) with substrates.
Tapeout designs with substrate suppliers and Intel teams.
Present designs and stay current with packaging tech.

Skills

High-speed signal routing

SI/PI considerations

Education

B.S. in Electrical Engineering or Computer Engineering

M.S. in Electrical Engineering or Computer Engineering

Tools

Siemens Xpedition

Job description

The role requires 5+ years of substrate design experience (or 3+ with MS) and hands-on Siemens Xpedition expertise, with opportunities to work on 2.5D/3D packaging and tapeouts in a cutting‑edge

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