Principal FPGA Architect - RF/EOIR & Secret Clearance

Northrop Grumman; United States; On-site; USD 120,000 - 224,000; Full time

Job summary

Northrop Grumman seeks Principal and Sr. Principal FPGA Design Engineers to join the MSTS division in Rolling Meadows, IL. You will lead end-to-end FPGA/EO-RF projects, from requirements through verification, timing closure, and production support, collaborating across systems, software, and hardware teams.

A secret clearance is required, and relocation assistance may be available. The roles require experience with FPGA device architectures (Xilinx/Intel), RTL languages, and development

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years FPGA/ASIC design experience (or advanced degrees with less).
• Proficiency in VHDL, Verilog, or SystemVerilog for RTL design.
• Experience translating requirements into FPGA architecture and verification criteria.
• Experience with synchronous RTL, state machines, pipelined data paths, and multi-clock domains.
• Proficiency with full FPGA development flow: RTL sim, synthesis, place & route, timing and power analysis.
• Experience reviewing timing reports and resolving timing-closure issues.
• Experience with vendor FPGA devices and toolchains (Xilinx or Intel), and related EDA tools.
• Programming/scripting in Python, Tcl, C/C++, or similar for automation and data analysis.
• Ability to work with cross-functional teams and communicate risks clearly.
• U.S. citizenship and interim Secret clearance required.

Responsibilities

• Contribute across the FPGA development lifecycle from requirements to production support.
• Develop FPGA-based digital subsystems integrated into circuit card assemblies.
• Collaborate with systems, software, hardware, and IT for end-to-end integration.
• Address timing, power, and resource constraints through optimization & verification.
• Lead technical reviews and mentor junior engineers when needed.

Skills

RTL design languages

FPGA development flow

Scripting: Python/Tcl/C/C++

Clock domain crossing

FPGA toolchains: Vivado/Quartus

System integration

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s or PhD (optional)

Tools

Vivado

Quartus

ModelSim/QuestaSim

Synplify

Job description

Northrop Grumman seeks Principal and Sr. Principal FPGA Design Engineers to join the MSTS division in Rolling Meadows, IL. You will lead end-to-end FPGA/EO-RF projects, from requirements through verification, timing closure, and production support, collaborating across systems, software, and hardware teams.

A secret clearance is required, and relocation assistance may be available. The roles require experience with FPGA device architectures (Xilinx/Intel), RTL languages, and development