Senior FPGA Digital Engineer - Secret Clearance

Northrop Grumman; Chandler (AZ); On-site; USD 108,000 - 162,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

Northrop Grumman Space Systems in Chandler, AZ seeks a Principal FPGA Digital Engineer to lead FPGA/SoC design efforts for the EO Group. You will develop and validate complex firmware with VHDL/Verilog, create and run advanced test benches, and ensure timing closure against stringent performance targets across hardware, algorithms, and software.

The role requires collaboration with cross-disciplinary teams, strong verification skills, and freedom to manage multiple design configurations.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline with 5 years of relevant experience; or Master’s degree with 3 years; or PhD with 1 year.
• Ability to obtain a U.S. DoD Secret security clearance at time of application.
• Solid FPGA/SoC design background with firmware development using VHDL (preferred) or Verilog.

Responsibilities

• Collaborate with senior FPGA engineers and multidisciplinary teams to resolve design and integration challenges.
• Develop and execute advanced test benches to verify FPGA designs meet functional and timing requirements.
• Generate, verify & integrate IO and image processing HDL modules, including definitions, coding, simulations, and integration.
• Ensure compliance with internal design standards throughout the development lifecycle.
• Oversee configuration management of multiple FPGA bitstream build configurations for different use cases.
• Prepare, present, and maintain design documentation, including schematics, simulation results, and verification reports.

Skills

FPGA/SoC design

VHDL/Verilog

Vivado

Vitis Unified IDE

OSVVM/UVM

Timing closure

Embedded C/C++

DDR interface design

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s degree in Electrical Engineering or Computer Engineering

PhD in related discipline

Tools

Vivado IDE

Vitis Unified IDE

Questa/ModelSim

Oscilloscopes

Logic analyzers

OSVVM

Job description

Northrop Grumman Space Systems in Chandler, AZ seeks a Principal FPGA Digital Engineer to lead FPGA/SoC design efforts for the EO Group. You will develop and validate complex firmware with VHDL/Verilog, create and run advanced test benches, and ensure timing closure against stringent performance targets across hardware, algorithms, and software.

The role requires collaboration with cross-disciplinary teams, strong verification skills, and freedom to manage multiple design configurations.