FPGA Design Engineer - Secret Clearance Eligible

Northrop Grumman; United States; On-site; USD 96,000 - 145,000; Full time

Benefits offered by this job

Relocation assistance

On-site role in Rolling Meadows, IL

Job summary

Northrop Grumman is seeking a talented FPGA Design Engineer for our MSTS division in Rolling Meadows, IL. This full-time, on-site role focuses on end-to-end development of RF and EO/IR products, contributing across RTL design, verification, and integration with cross-functional teams.

The role requires a bachelor’s degree in Electrical/Computer Engineering or related field and at least 2 years of FPGA/ASIC experience, with VHDL/Verilog/SystemVerilog proficiency and Vivado/Quartus expertise. U.S.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or closely related engineering discipline.
• Minimum of 2 years FPGA/ASIC design experience.
• Solid understanding of VHDL, Verilog, or SystemVerilog for RTL design and verification.
• Experience with RTL design, testbenches, and debugging simulation failures.
• Familiarity with FPGA development flow and toolchains (Vivado/Quartus).
• Experience with scripting languages (MATLAB/Python/C/C++).
• Ability to work across engineering disciplines with proactive communication.

Responsibilities

• Contribute across end-to-end FPGA/EO/IR product development lifecycle.
• Develop FPGA-based digital subsystems integrated into circuit card assemblies.
• Collaborate with systems, software, hardware, and test engineers.
• Translate requirements into RTL architecture, timing, and verification.

Skills

FPGA design

RTL design

HDL languages

C/C++

Python

MATLAB

Education

Electrical/Computer Engineering degree

Tools

Vivado

Quartus

ModelSim/QuestaSim

SOPC Builder/Qsys/Platform Designer

Synplify

Job description

Northrop Grumman is seeking a talented FPGA Design Engineer for our MSTS division in Rolling Meadows, IL. This full-time, on-site role focuses on end-to-end development of RF and EO/IR products, contributing across RTL design, verification, and integration with cross-functional teams.

The role requires a bachelor’s degree in Electrical/Computer Engineering or related field and at least 2 years of FPGA/ASIC experience, with VHDL/Verilog/SystemVerilog proficiency and Vivado/Quartus expertise. U.S.