Principal FPGA Engineer – Secret-Clearance, On‑Site Role

Northrop Grumman; Rolling Meadows (IL); Presencial; USD 120.000 - 224.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

Life and disability insurance

Savings plan

Company paid holidays and PTO

Descripción de la vacante

Northrop Grumman in Rolling Meadows, IL seeks talented Principal and Sr. Principal FPGA Design Engineers to lead end-to-end FPGA development for RF and EO/IR products. You will work with FPGA architectures, RTL, verification, synthesis, and hardware integration in a collaborative, high-performing team.

The role requires a Bachelor’s in Electrical/Computer Engineering with 5+ (Principal) or 8+ (Sr. Principal) years of FPGA/ASIC experience, proficiency in VHDL/Verilog/SystemVerilog, and U.S.

Formación

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or closely related field; 5+ years FPGA/ASIC design for Principal.
• Experience with VHDL, Verilog or SystemVerilog for RTL.
• Experience translating requirements into FPGA architecture and verification criteria.
• Experience with full FPGA development flow and timing closure.

Responsabilidades

• Develop FPGA-based subsystems across the end-to-end lifecycle.
• Collaborate with systems, software, and hardware teams; support integration and testing.
• Provide technical leadership and drive architectural decisions for complex FPGA projects.

Conocimientos

RTL design

VHDL/Verilog

Python

C/C++

SystemVerilog

Clock domain

Verification

Team collaboration

Educación

BS in Electrical/Computer Engineering

Herramientas

Vivado

Quartus

ModelSim

QuestaSim

Synplify

Descripción del empleo

Northrop Grumman in Rolling Meadows, IL seeks talented Principal and Sr. Principal FPGA Design Engineers to lead end-to-end FPGA development for RF and EO/IR products. You will work with FPGA architectures, RTL, verification, synthesis, and hardware integration in a collaborative, high-performing team.

The role requires a Bachelor’s in Electrical/Computer Engineering with 5+ (Principal) or 8+ (Sr. Principal) years of FPGA/ASIC experience, proficiency in VHDL/Verilog/SystemVerilog, and U.S.