Lead Front-End SoC Design Engineer (PCIe/Ethernet)

Hardware FYI; San Jose, Northern (CA, KY); Hybrid; USD 185,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal Digital Design Engineer in the United States to lead front-end circuit design, RTL, and verification for high‑performance network controllers. You will own architecture‑to‑GDSII delivery and work with teams to meet tight timing on advanced CMOS processes.

The role requires hands‑on experience with PCIe, ULink, Esun, Ethernet, and strong front‑end design, verification, and test expertise. UVM familiarity and US work authorization are preferred.

Qualifications

• Bachelor's degree in Electrical Engineering required; Master's preferred.
• +8 years’ experience in complex SoC/silicon products for Switch ASIC/Networking/Server.
• Experience with front-end design, RTL, verification, timing, and DFT.
• Proficiency with high-speed protocols (PCIe, Ualink, Esun, Ethernet).

Responsibilities

• Lead front-end design from architecture to GDS, delivering complex designs to production.
• Perform RTL, simulations, synthesis, and timing closure.
• Drive design-for-test and UVM-based verification.
• Collaborate with cross-functional teams and customers to meet requirements.

Skills

Front-end design

RTL

Synthesis

DFT

UVM

Timing closure

PCIe

ULink

Hardware verification

Silicon bring-up

Education

Bachelor's degree in EE

Master's degree

Tools

Synopsys tools

Cadence tools

Job description

Astera Labs is seeking a Principal Digital Design Engineer in the United States to lead front-end circuit design, RTL, and verification for high‑performance network controllers. You will own architecture‑to‑GDSII delivery and work with teams to meet tight timing on advanced CMOS processes.

The role requires hands‑on experience with PCIe, ULink, Esun, Ethernet, and strong front‑end design, verification, and test expertise. UVM familiarity and US work authorization are preferred.