Remote ASIC Design Engineer for AI Inference Accelerators

Tensordyne; Sunnyvale (CA); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Flexible spending

Bonusly awards

Health benefits

Financial security

Job summary

Tensordyne, a Sunnyvale-based AI ASIC startup, seeks an experienced ASIC design engineer to drive microarchitecture and RTL implementation for a high-performance CNN accelerator ASIC. You will integrate CPU and IP blocks, collaborate with physical design, and support timing closure at high frequencies.

The role requires 3+ years in ASIC design with Verilog/SystemVerilog, knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, and AMBA protocols. A BS/MS in EE/CE is preferred.

Qualifications

• 3+ years of ASIC design experience with RTL in multi-million gate ASICs.
• Experience in IP integration, particularly CPU IP into SoC.
• Knowledge of ARM/RISC-V/MIPS architectures and AMBA protocols.
• Familiarity with UPF-based power intent and timing closure.

Responsibilities

• Author/understand micro-architecture specs and participate in test plans.
• Integrate CPU and other IPs into the CPU sub-system.
• Collaborate with physical design to resolve timing issues and optimize power.
• Perform diagnostic tests and assist software bring-up in the lab.

Skills

ASIC design

RTL design

Verilog/SystemVerilog

IP integration

ARM/RISC-V/MIPS

Timing closure

Power-aware design

Education

Electrical or Computer Engineering - BS/MS

Tools

EDA toolchain

Place-and-route tools

Job description

Tensordyne, a Sunnyvale-based AI ASIC startup, seeks an experienced ASIC design engineer to drive microarchitecture and RTL implementation for a high-performance CNN accelerator ASIC. You will integrate CPU and IP blocks, collaborate with physical design, and support timing closure at high frequencies.

The role requires 3+ years in ASIC design with Verilog/SystemVerilog, knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, and AMBA protocols. A BS/MS in EE/CE is preferred.