Lead ASIC RTL Design Engineer

10xTalents; San Francisco (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

A technology company is seeking a senior-level Lead ASIC RTL Design Engineer to develop high-performance silicon components for advanced compute platforms. This role involves defining microarchitecture, leading front-end design, and guiding less experienced engineers. The ideal candidate will have over 8 years of experience in ASIC design, strong skills in System Verilog, and a Bachelor's or Master's degree in Electrical/Computer Engineering. The position is remote, based in the U.S., and does not offer visa sponsorship.

Qualifications

• 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices.
• Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness.
• Strong System Verilog expertise.

Responsibilities

• Define microarchitecture for complex subsystems and document design specifications.
• Lead front-end design activities including linting and synthesis readiness.
• Design and integrate high-bandwidth interfaces.

Skills

System Verilog expertise

Communication skills

Technical leadership

Front-end design tools

Education

Bachelor's or Master's degree in Electrical or Computer Engineering

Tools

Python

Tcl

Job description

Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship

Role Summary

Our client, a leader in AICompute isseeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.

Core Responsibilities

Architecture & RTL Development

• Define microarchitecture for complex subsystems and document design specifications
• Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
• Incorporate assertions and design-for-debug features within RTL

Design Ownership & Implementation

• Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
• Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
• Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks

High-Speed Interfaces & Memory Systems

• Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
• Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
• Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality

Engineering Processes & Tooling

• Establish and maintain RTL design standards, reusable components, and signoff criteria
• Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)

Collaboration & System Integration

• Partner with verification teams on test planning, coverage goals, and model alignment
• Work with architecture and performance engineering to validate design intent against system-level expectations
• Support silicon bring-up, debugging, and downstream customer or system integration efforts

Technical Leadership

• Mentor less experienced engineers and provide guidance on design best practices
• Lead design reviews and help drive key technical decisions across teams
• Advocate for scalable, efficient, and high-quality engineering solutions

Basic Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
• 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
• Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
• Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
• Hands‑on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
• Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
• Strong communication skills with the ability to lead technical discussions and document designs clearly

Preferred Experience

• Exposure to AI/ML hardware or high-performance compute architectures
• Knowledge of formal verification techniques and assertion-based design
• Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
• Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
• Understanding of modern processor subsystems, coherence models, or custom tool flows