Staff ASIC Design Engineer: RTL & Silicon BringUp On-site

SiMa.ai, Inc.; San Jose, Northern (CA, KY); Hybride; USD 137 000 - 219 000; Plein temps

Résumé du poste

SiMa.ai, Inc. in San Jose, CA is seeking a Staff ASIC Design Engineer to own complex blocks from microarchitecture and RTL through verification and silicon bring-up.

This full-time, on-site role requires expert RTL (Verilog/SystemVerilog), strong block-level optimization, and collaboration with verification, physical design, architecture, and firmware teams to meet timing, power, and area targets. Salary ranges from $136,900 to $219,000.

Qualifications

• Master's degree required in EE/CE or related field.
• 5+ years of ASIC design experience focusing on block-level RTL.
• Experience taking blocks from microarchitecture to silicon.
• Experience with RTL design, synthesis, timing closure, and DFT concepts.

Responsabilités

• Own microarchitecture definition and RTL implementation of complex blocks.
• Drive ground-up block design from specification to silicon.
• Develop high-quality, synthesizable RTL in Verilog/SystemVerilog.
• Collaborate with verification, physical design, architecture, and firmware teams to meet timing, power, and area targets.
• Drive block-level synthesis, timing closure, and DFT readiness.

Connaissances

RTL design

Microarchitecture

Synthesis

Timing closure

DFT concepts

Data-path optimization

Formation

Master's degree in Electrical Engineering, Computer Engineering, or related field

Outils

Verilog/SystemVerilog

Synthesis tools

DFT tooling

Description du poste

SiMa.ai, Inc. in San Jose, CA is seeking a Staff ASIC Design Engineer to own complex blocks from microarchitecture and RTL through verification and silicon bring-up.

This full-time, on-site role requires expert RTL (Verilog/SystemVerilog), strong block-level optimization, and collaboration with verification, physical design, architecture, and firmware teams to meet timing, power, and area targets. Salary ranges from $136,900 to $219,000.