Lead ASIC Design Engineer – High-Performance Networking

Hewlett Packard Enterprise Development LP; Sunnyvale (CA); Hybride; USD 174 000 - 353 000; Plein temps

Avantages offerts par ce poste

Health & Wellbeing

Professional development

Inclusive culture

Hybrid work model

Résumé du poste

Hewlett Packard Enterprise Development LP in Sunnyvale, CA, seeks a Principal ASIC Design Engineer to architect high-performance networking chip modules. You will specify, implement, and verify RTL in Verilog/SystemVerilog, craft coverage plans, and drive power-conscious designs.

Lead cross-functional teams with a focus on timing closure and quality. The role requires 15+ years of experience, a strong background in ASIC design, and excellent communication.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent required.
• 15+ years of relevant experience with strong Verilog/SystemVerilog knowledge.
• Experience leading high-performance ASIC design projects and mentoring engineers.

Responsabilités

• Architect complex modules and subsystems for high-performance networking chips.
• Write detailed functional and micro-architecture specifications.
• Implement designs using Verilog or SystemVerilog; develop tests and coverage.
• Create functional coverage/SVA to catch corner cases.
• Ensure power targets with advanced techniques; collaborate with physical design for timing closure.
• Coordinate with verification; provide leadership to new engineers and interns.

Connaissances

Verilog/SystemVerilog

Python

Perl

Leadership

Analytical thinking

Formation

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Outils

Synthesis tools

Description du poste

Hewlett Packard Enterprise Development LP in Sunnyvale, CA, seeks a Principal ASIC Design Engineer to architect high-performance networking chip modules. You will specify, implement, and verify RTL in Verilog/SystemVerilog, craft coverage plans, and drive power-conscious designs.

Lead cross-functional teams with a focus on timing closure and quality. The role requires 15+ years of experience, a strong background in ASIC design, and excellent communication.