Hybrid ASIC Design Engineer – High-Speed Networking

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 124,000 - 251,000; Full time

Benefits offered by this job

Hybrid work model

Health & wellbeing benefits

Career development

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA seeks an ASIC Design Engineer to build high-speed networking chips. You'll develop modules from spec to RTL, working with verification and physical design teams to meet timing and power targets.

This hybrid role requires a strong background in Verilog/SystemVerilog, EDA tools, and collaboration across teams; the ideal candidate holds a bachelor’s in electrical engineering with 4+ years of relevant experience, and is ready to mentor newer engineers.

Qualifications

• Bachelor’s degree in Electrical Engineering with 4+ years in ASIC/SoC design.
• Strong Verilog/SystemVerilog coding skills and circuit design knowledge.
• Experience with EDA tools and timing closure.

Responsibilities

• Develop functional specifications and micro-architecture for ASIC modules.
• Implement designs using Verilog/SystemVerilog and verify with testbenches.
• Collaborate with Physical Design for floorplanning and timing.
• Mentor new graduates and interns.

Skills

Verilog/SystemVerilog coding

Analytical/problem solving

Networking protocols knowledge

Python/Perl scripting

Communication skills

Education

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Tools

EDA tools

Job description

Hewlett Packard Enterprise in Sunnyvale, CA seeks an ASIC Design Engineer to build high-speed networking chips. You'll develop modules from spec to RTL, working with verification and physical design teams to meet timing and power targets.

This hybrid role requires a strong background in Verilog/SystemVerilog, EDA tools, and collaboration across teams; the ideal candidate holds a bachelor’s in electrical engineering with 4+ years of relevant experience, and is ready to mentor newer engineers.