Principal ASIC Design Engineer (AI Hardware)

Upscale; Kentucky; On-site; USD 120,000 - 170,000; Full time

Job summary

Upscale, Inc. is hiring an ASIC Design engineer to define micro-architecture and deliver RTL that meets power, performance, and area targets. You will collaborate with verification, emulation, and physical design teams to ensure robust timing closure and area optimization.

The role requires strong SystemVerilog expertise, deep understanding of clock domain crossing and synthesis. Excellent communication and teamwork in a fast-paced startup environment are essential.

Qualifications

• BE or MS in EE, CE, CS.
• 5+ years of related technical engineering experience.
• 5+ years of industry experience in logic design on complex ASICs.
• Experience with SystemVerilog for logic design.
• Understanding of logic design, clock domain crossing, synthesis and timing closure.
• Proficient communication, collaboration and teamwork skills.
• Able to thrive or lead in a fast-paced startup environment.

Responsibilities

• Define and document micro-architecture for next generation designs with architecture team.
• Design RTL that meets power, performance, and area targets.
• Collaborate with verification and emulation teams to ensure test plans meet architecture intent.
• Work with physical design on timing closure and area optimization.
• Integrate DFT logic with design-for-test team.
• Communicate effectively and collaborate with cross-functional teams.

Skills

SystemVerilog

Logic design

ASICs

Clock domain crossing

Synthesis & timing closure

Communication & teamwork

Startup environment

Education

BE/MS in EE/CE/CS

Tools

LINT

CDC

RDC

Job description

Upscale, Inc. is hiring an ASIC Design engineer to define micro-architecture and deliver RTL that meets power, performance, and area targets. You will collaborate with verification, emulation, and physical design teams to ensure robust timing closure and area optimization.

The role requires strong SystemVerilog expertise, deep understanding of clock domain crossing and synthesis. Excellent communication and teamwork in a fast-paced startup environment are essential.