Senior ASIC Verification Engineer for AI-Scale Systems

Upscale, Inc.; Kentucky; On-site; USD 212,000 - 246,000; Full time

Job summary

Upscale, Inc. is building high-performance infrastructure for AI workloads. The role focuses on verifying complex ASIC designs, using SystemVerilog, UVM, ABV, and formal methods, across block- and system-level projects in a fast-paced environment.

You will collaborate with design and cross-functional teams to improve test generation, coverage, and debug productivity, contributing to scalable verification infrastructure and reusable IP.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years industry experience or Master's with 7+ years relevant experience.
• Proven experience verifying complex ASIC designs at block and system levels.
• Strong proficiency with SystemVerilog and UVM.
• Extensive knowledge of ASIC design verification methodologies and best practices.
• Experience collaborating with cross-functional teams from architecture to FCS.
• Strong programming and scripting skills in C, C++, and/or Python.
• Excellent debugging and root-cause analysis skills.

Responsibilities

• Design, develop, and maintain verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.
• Develop verification plans and create test cases for functional coverage.
• Verify RTL designs at block and chip levels using directed testing, constrained-random verification, ABV, formal verification, and functional coverage techniques.
• Perform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations.
• Debug and resolve design and verification issues with cross-functional teams.
• Drive adoption of advanced verification methodologies and automation frameworks.
• Apply data-driven analytics and AI-assisted techniques to improve test generation and regression productivity.
• Continuously improve verification processes, infrastructure, and reusable IP.

Skills

SystemVerilog

UVM

ASIC verification

C/C++

Python

Debugging

Regression management

ABV

Constrained-random

Formal verification

Ethernet

PCIe

Switch fabric

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science

Master's degree in Electrical Engineering / Computer Engineering

Tools

Verilog simulators

Job description

Upscale, Inc. is building high-performance infrastructure for AI workloads. The role focuses on verifying complex ASIC designs, using SystemVerilog, UVM, ABV, and formal methods, across block- and system-level projects in a fast-paced environment.

You will collaborate with design and cross-functional teams to improve test generation, coverage, and debug productivity, contributing to scalable verification infrastructure and reusable IP.