Senior ASIC Modeling Engineer for AI Networking

Upscale, Inc.; United States; On-site; USD 159,000 - 178,000; Full time

Job summary

Upscale, Inc. is building a simulation platform for next‑gen AI networking ASICs, delivering a functionally accurate software model of our ASIC architecture to support software development, verification, and customer validation before silicon is available.

You will develop, test, and maintain the platform across multiple ASIC generations, ensuring hardware‑accurate behavior and scalable simulations for demanding AI workloads.

Qualifications

• 7+ years of experience in C/C++ architecture model development or ASIC verification.
• Deep understanding of network switch/router architecture: forwarding tables, scheduling, QoS, ACLs.
• Experience with packet processing pipelines and dataplane simulation.
• Familiarity with hardware description languages (Verilog/SystemVerilog) and reading RTL.
• Experience with IPC mechanisms (gRPC/Protobuf).
• Experience with C++ unit testing (Google Test).
• Familiarity with Python for test automation and scripting.

Responsibilities

• Design and implement software model components that simulate ASIC behavior.
• Translate architectural specs into high-fidelity C++ models.
• Develop and maintain the register model, memory map, and configuration interfaces.
• Implement packet processing pipelines for multiple forwarding modes.
• Optimize model performance for large-scale simulations.
• Collaborate with RTL engineers to ensure model-to-silicon correlation.
• Work with architecture team to validate algorithm and architectural choices.
• Support SDK and platform teams to validate on the model.
• Maintain support for multiple ASIC versions with configurable architecture.

Skills

C++

Architecture model development

Cycle-aware simulation

ASIC verification

Networking hardware

Python for tooling

Debugging across hardware/software

Tools

Verilog

SystemVerilog

gRPC

Protobuf

Job description

Upscale, Inc. is building a simulation platform for next‑gen AI networking ASICs, delivering a functionally accurate software model of our ASIC architecture to support software development, verification, and customer validation before silicon is available.

You will develop, test, and maintain the platform across multiple ASIC generations, ensuring hardware‑accurate behavior and scalable simulations for demanding AI workloads.