Senior ASIC Simulation Engineer – AI Hardware Platform

Upscale, Inc.; Kentucky; On-site; USD 159,000 - 178,000; Full time

Job summary

Upscale, Inc. is building the simulation platform for its next-generation AI networking ASICs.

The role focuses on developing, testing, and maintaining a functionally accurate software model that mirrors hardware behavior across multiple ASIC generations, enabling software development, verification, and customer validation before silicon is available. Youll translate architectural specifications into high-fidelity C++ models, optimize for large-scale simulations, and ensure model-to-silicon

Qualifications

• 7+ years of experience in C/C++ architecture model development, cycle-aware simulation, or ASIC verification.
• Expert-level C++ programming (modern C++17).
• Deep understanding of network switch/router architecture and QoS.
• Experience with gRPC, Protocol Buffers or IPC mechanisms.
• Familiarity with Verilog/SystemVerilog and RTL reading.

Responsibilities

• Design and implement software model components that accurately simulate ASIC behavior.
• Translate architectural specifications into high-fidelity C++ models.
• Develop and maintain the register model, memory map, and configuration interfaces.
• Implement packet processing pipelines for multiple forwarding modes.
• Optimize model performance for large-scale simulations.
• Collaborate with RTL engineers to ensure model-to-silicon correlation.
• Work with architecture teams to validate algorithm choices via simulation.
• Coordinate with SDK and platform teams to enable development on the model.
• Support multiple ASIC versions with maintainable, configurable model architecture.

Skills

C/C++ architecture modeling

Cycle-aware simulation

ASIC verification

Verilog/SystemVerilog

gRPC/Protobuf

Google Test

Python scripting

Tools

Verilog/SystemVerilog

gRPC

Protocol Buffers

NS-3 / HTSim

FPGA prototyping

Job description

Upscale, Inc. is building the simulation platform for its next-generation AI networking ASICs.

The role focuses on developing, testing, and maintaining a functionally accurate software model that mirrors hardware behavior across multiple ASIC generations, enabling software development, verification, and customer validation before silicon is available. Youll translate architectural specifications into high-fidelity C++ models, optimize for large-scale simulations, and ensure model-to-silicon