Senior AI ASIC Verification Engineer

Upscale; Kentucky; On-site; USD 180,000 - 260,000; Full time

Job summary

Upscale, Inc. is building high-performance infrastructure powering the next generation of AI workloads in the United States.

We offer a challenging role focused on robust verification environments, testbenches, and reference models for ASIC designs at block and system levels, with a strong emphasis on quality, performance, and scalability. Ideal candidates bring 7+ years of ASIC verification experience, proficiency in SystemVerilog/UVM, and strong C/C++/Python skills.

Qualifications

• Bachelor’s or Master’s degree with 7–10+ years in ASIC verification.
• Proven experience verifying complex ASIC designs at block and system levels.
• Strong programming in C, C++, Python.
• Proficiency with SystemVerilog and UVM.
• Experience with ABV, constrained-random verification, and regression management.

Responsibilities

• Design, develop, and maintain verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.
• Develop verification plans and create test cases to ensure functional coverage.
• Verify RTL designs at block and chip levels using directed testing and constrained-random verification.
• Perform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations.
• Debug and resolve design and verification issues with cross-functional teams.
• Drive adoption of advanced verification methodologies and automation frameworks.
• Apply data-driven analytics and AI-assisted techniques to improve test generation, regression analysis, and debug productivity.
• Continuously improve verification processes and reusable IP to speed up development cycles.

Skills

SystemVerilog

UVM

C/C++

Python

Debugging

Verification planning

ABV

Education

Bachelor’s degree in Electrical/Computer Engineering or Computer Science

Master’s degree in related field

Job description

Upscale, Inc. is building high-performance infrastructure powering the next generation of AI workloads in the United States.

We offer a challenging role focused on robust verification environments, testbenches, and reference models for ASIC designs at block and system levels, with a strong emphasis on quality, performance, and scalability. Ideal candidates bring 7+ years of ASIC verification experience, proficiency in SystemVerilog/UVM, and strong C/C++/Python skills.