ASIC Design - Principal Engineer

Upscale; Kentucky; On-site; USD 120,000 - 170,000; Full time

Job summary

Upscale, Inc. is hiring an ASIC Design engineer to define micro-architecture and deliver RTL that meets power, performance, and area targets. You will collaborate with verification, emulation, and physical design teams to ensure robust timing closure and area optimization.

The role requires strong SystemVerilog expertise, deep understanding of clock domain crossing and synthesis. Excellent communication and teamwork in a fast-paced startup environment are essential.

Qualifications

• BE or MS in EE, CE, CS.
• 5+ years of related technical engineering experience.
• 5+ years of industry experience in logic design on complex ASICs.
• Experience with SystemVerilog for logic design.
• Understanding of logic design, clock domain crossing, synthesis and timing closure.
• Proficient communication, collaboration and teamwork skills.
• Able to thrive or lead in a fast-paced startup environment.

Responsibilities

• Define and document micro-architecture for next generation designs with architecture team.
• Design RTL that meets power, performance, and area targets.
• Collaborate with verification and emulation teams to ensure test plans meet architecture intent.
• Work with physical design on timing closure and area optimization.
• Integrate DFT logic with design-for-test team.
• Communicate effectively and collaborate with cross-functional teams.

Skills

SystemVerilog

Logic design

ASICs

Clock domain crossing

Synthesis & timing closure

Communication & teamwork

Startup environment

Education

BE/MS in EE/CE/CS

Tools

LINT

CDC

RDC

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

Job Responsibilities:

• As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs.
• Responsible for the logic design/RTL entry that meets the power, performance, area targets.
• Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure
• Work closely with the physical design team on timing closure and area optimization
• Work with the design for test team to integrate DFT logic
• Work independently, communicate effectively and collaborate with cross functional teams

Requirements:

• BE or MS in EE, CE, CS
• 5+ years of related technical engineering experience
• 5+ years of industry experience in logic design on complex ASICs
• Experience with SystemVerilog for logic design
• Understanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure
• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
• Able to thrive or lead in a fast-paced startup environment

Preferred:

• 12+ years of relevant industry experience with a proven track record of successful tapeouts
• Scripting proficiency using Python, Perl etc.
• Experience with front end design tools like LINT, CDC, RDC
• Exposure to silicon bring-up
• Analyzing timing, area, power reports and ability to drive design fixesKnowledge of verification principles and coverage and ability to debug complex test cases
• Basic understanding of formal verification
• Past work experience on high performance, low latency networking ASICs is a big plus
• Growth mindset and enthusiasm to learn and grow in a fast paced environment

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.