Pre-Silicon Verification Engineer - SystemVerilog

Wipro; Santa Clara (UT); On-site; USD 60,000 - 148,500; Full time

Benefits offered by this job

Medical and dental benefits

Disability insurance

Paid time off

Other paid and unpaid leave options

Job summary

A global technology consulting firm seeks a candidate to architect and develop complex verification environments using SystemVerilog. The role requires 5-8 years of experience, exposing candidates to RTL design and formal verification tools like VCS, Cadence, and Mentor Graphics. This position offers a salary range of $60,000 to $148,500, depending on various factors, and includes full medical and dental benefits, disability insurance, and paid time off.

Qualifications

• 5-8 years of experience in relevant fields.
• Experience with scripting in Perl, Ruby, Make.

Responsibilities

• Architect and develop complex verification environments in SystemVerilog.
• Conduct exposure to RTL design and software development.
• Utilize formal verification tools.

Skills

Pre-silicon Validation

SystemVerilog

Education

Bachelor's or Master’s degree in computer engineering/Electrical Engineering

Tools

VCS

Cadence

Mentor Graphics

Job description

A global technology consulting firm seeks a candidate to architect and develop complex verification environments using SystemVerilog. The role requires 5-8 years of experience, exposing candidates to RTL design and formal verification tools like VCS, Cadence, and Mentor Graphics. This position offers a salary range of $60,000 to $148,500, depending on various factors, and includes full medical and dental benefits, disability insurance, and paid time off.