Silicon Verification Engineer (SystemVerilog/UVM)

Google LLC; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC in Mountain View, CA is seeking a Design Verification Engineer to advance silicon verification across complex SoCs. You will collaborate with design, software and hardware teams to define verification strategies and environments, and contribute to tape-out readiness.

Requires a Bachelor's in EE/CE/CS and 4 years of experience with SystemVerilog and UVM, plus experience with AXI/APB/ACE protocols and building verification test benches.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 4 years of verification experience with SystemVerilog and UVM.
• Experience with AXI, APB, and ACE protocols.
• Experience building verification test benches and environments.

Responsibilities

• Plan verification strategies for complex digital design blocks in collaboration with design engineers.
• Build constrained-random verification environments using SystemVerilog and UVM.
• Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
• Debug test failures with design engineers to ensure functional correctness.
• Drive coverage closure toward tape-out milestones.

Skills

Verification methodologies

Interdisciplinary collaboration

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science or related field

Tools

SystemVerilog

UVM

AXI

APB

ACE

Job description

Google LLC in Mountain View, CA is seeking a Design Verification Engineer to advance silicon verification across complex SoCs. You will collaborate with design, software and hardware teams to define verification strategies and environments, and contribute to tape-out readiness.

Requires a Bachelor's in EE/CE/CS and 4 years of experience with SystemVerilog and UVM, plus experience with AXI/APB/ACE protocols and building verification test benches.