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Benefits offered by this job
Comprehensive medical and dental coverage
Employee stock programs
Tuition reimbursement for education
Job summary
A leading technology company in California is seeking a motivated design verification engineer to enhance their silicon development processes. This role focuses on creating comprehensive verification methodologies, with a strong emphasis on SystemVerilog and UVM, ensuring the development of efficient test environments. Ideal candidates will possess solid backgrounds in verification methods and have experience with both serial and parallel protocols. Competitive salary, stock options, and extensive benefits included.
Qualifications
Deep experience in SystemVerilog and UVM methodologies.
Background in creating scalable test-benches and verification plans.
Experience in using simulators and waveform viewers.
Responsibilities
Study design specifications and create comprehensive test plans.
Develop infrastructure in SystemVerilog/UVM to stress the design.
Debug failures from regressions and improve test outcomes.
Skills
Deep knowledge of SystemVerilog
Knowledge in developing scalable and portable test-benches
Experience with verification methodologies and tools
Proficient in automation and coverage collection
Familiarity with C/C++
Experience with serial protocols such as PCIe or USB
Knowledge of scripting languages such as Python
Job description
A leading technology company in California is seeking a motivated design verification engineer to enhance their silicon development processes. This role focuses on creating comprehensive verification methodologies, with a strong emphasis on SystemVerilog and UVM, ensuring the development of efficient test environments. Ideal candidates will possess solid backgrounds in verification methods and have experience with both serial and parallel protocols. Competitive salary, stock options, and extensive benefits included.