Senior SOC Physical Design Engineer — Power & Timing Lead

Qualcomm; Austin (TX); On-site; USD 152,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. in Austin, Texas is seeking a Staff SOC Physical Design Engineer to lead the physical design flow for high-speed DDR, graphics, and SOC components, with emphasis on target power utilization and performance.

The role covers floor planning, clock tree, place and route, PDN and timing closure, plus verification checks and cross-functional collaboration to drive tapeout readiness.

Qualifications

• Master's degree or foreign academic equivalent required.
• 3 years of related occupation experience.

Responsibilities

• Lead the physical design flows for DDR, graphics, and SOC, focusing on target power utilization and performance.
• Perform LVS/DRC/DFM and design-for-manufacturing & design-for-yield checks at chip and block levels.
• Provide schedules and cross-functional support to drive signoff for tapeout.
• Contribute to design reviews and project meetings and implement development plans.

Skills

Physical design flow

Floor Planning

Place and Route

Timing analysis

Power optimization

Signal integrity

Education

Master's degree in Electrical Engineering / Computer Engineering / Computer Science or related field

Tools

LVS/DRC tools

EDA tools

Job description

Qualcomm Technologies, Inc. in Austin, Texas is seeking a Staff SOC Physical Design Engineer to lead the physical design flow for high-speed DDR, graphics, and SOC components, with emphasis on target power utilization and performance.

The role covers floor planning, clock tree, place and route, PDN and timing closure, plus verification checks and cross-functional collaboration to drive tapeout readiness.